The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
One development in the scaling down process is fabricating fin-type field effect transistors (FinFETs). It is desired to further improve the operation of fabricating the FinFETs, such as by using a high etch selectivity material as an inter-layer dielectric (ILD) hard mask layer to prevent ILD loss in various fabrication processes. Accordingly, what is needed is a method for improving the fabrication and operation of the FinFET.